A "testable" design is one that simplifies the process of identifying defects introduced during manufacturing or failures occurring during operation. The definitive text on this subject, Digital Systems Testing and Testable Design
: Models an accidental short circuit between two or more signal nets. The resulting behavior can be wired-AND, wired-OR, or dominant logic depending on the technology node. Dynamic and Parametric Fault Models
The Q-90's package was a 1,500-ball BGA. No physical probes. They'd use JTAG (IEEE 1149.1) boundary scan to shift test data in and out through the existing debug port. The silicon was already wired for it—the designer just forgot to use it for internal faults. A "testable" design is one that simplifies the
Engineers write clean hardware description code (Verilog/VHDL) while following structural rules, such as avoiding uncontrollable internal clocks, asynchronous resets, and tri-state bus contentions.
With billions of transistors, storing raw test patterns requires massive ATE memory and long test times, inflating production costs. Deploying embedded compression technologies (like Synopsys TestMAX or Siemens Tessent) allows test patterns to be decompressed on-chip into thousands of internal scan chains and compressed back down for the tester, reducing test time and data volume by orders of magnitude without sacrificing fault coverage. 3. Comprehensive Fault Simulation Dynamic and Parametric Fault Models The Q-90's package
Converts sequential testing into simple combinational testing. Increased silicon area and higher pin counts. Allows chips to test themselves without external machinery. Complex logic overhead and increased power consumption. Boundary Scan (IEEE 1149.1) Simplifies board-level interconnect testing. Added delay on critical high-speed input/output paths.
Consider an ADAS controller chip (16nm, 200M gates, 500MB memory). The requirement: ( < 1 DPPM). The silicon was already wired for it—the designer
Used for in-field testing (automotive diagnostics) or high-speed memory testing.
Generates pseudorandom input patterns natively at hardware speeds.